1. Technical Field
The embodiment described herein relates to a semiconductor memory apparatus and, more particularly, to a circuit for generating a power-up signal.
2. Related Art
A power-up signal, as a signal for initializing a semiconductor memory apparatus, is enabled when an external voltage is applied to the semiconductor memory apparatus and the level of the external voltage is higher than a predetermined level. At this time, the semiconductor memory apparatus performs an initialization operation during a disable interval of the power-up signal.
As shown in FIG. 1, a conventional circuit for generating a power-up signal can be configured to include first and second resistors R1 and R2, first and second transistors P1 and N1, and an inverter IV1.
The first and second resistors R1 and R2 are connected to each other in series and respectively applied with an external voltage VDD and a ground voltage VSS at terminals thereof. At this time, a divided voltage ‘V_dv’ is outputted from a node that is connected to the first resistor R1 and the second resistor R2.
The first transistor P1 is applied with the ground voltage VSS at a gate thereof and applied with the external voltage VDD at a source thereof.
The second transistor N1 is applied with the divided voltage ‘V_dv’ at a gate thereof, connected to a drain of the first transistor P1 at a drain thereof, and applied with the ground voltage VSS at a source thereof.
The inverter IV1 enables a power-up signal ‘pwrup’ at a high level when a voltage level of a node ‘node A’ that is connected to the first transistor P1 and the second transistor N2 is lower than a predetermined voltage level.
An operation of the conventional circuit for generating the power-up signal of the semiconductor memory apparatus will be described below.
As the level of the external voltage VDD increases, the level of the divided voltage ‘V_dv’ also increases.
The voltage level of the node ‘node A’ also increases through the first transistor P1.
As the voltage level of the node ‘node A’ increases, the inverter IV1 outputs the power-up signal ‘pwrup’ disabled at a low level.
As the level of the external voltage VDD increases, the level of the divided voltage ‘V_dv’ increases to turn on the second transistor N1, such that the second transistor N1 is turned on.
As the second transistor N1 is turned on, the voltage level of the node ‘node A’ decreases.
When the voltage level of the node ‘node A’ is equal to or lower than a predetermined voltage level, the inverter IV1 generates the power-up signal ‘pwrup’ enabled at a high level.
As shown in FIG. 2, the conventional circuit for generating the power-up signal, which operates as above has a disadvantage in that an enable timing of the power-up signal ‘pwrup’ varies.
More specifically, when a threshold voltage of the first transistor P1 is higher than a threshold voltage designed or a threshold voltage of the second transistor N1 is lower than the threshold voltage designed, the enable timing ‘a’ of the power-up signal ‘pwrup’ is earlier than a normal enable timing ‘c’.
When the threshold voltage of the first transistor P1 is lower than the threshold voltage designed or the threshold voltage of the second transistor N1 is higher than the threshold voltage designed, the enable timing ‘b’ of the power-up signal ‘pwrup’ is later than the normal enable timing ‘c’.
That is, the conventional circuit for generating the power-up signal of the general semiconductor memory apparatus has a disadvantage in that the enable timing of the power-up signal varies depending on variation in the process at the time of fabricating the circuit for generating the power-up signal. When the enable timing of the power-up signal is earlier or later than the normal timing, the semiconductor memory apparatus may be mis-operated because an initialization operation of the semiconductor memory apparatus is not normally performed.